The present invention relates to a semiconductor memory device and more specifically to a technique suitably applied to a semiconductor memory device using a memory cell formed of a ferroelectric capacitor and an address selection MOSFET.
Examples of semiconductor memory devices, that use ferroelectric capacitors as memory cells and which can switch between a non-volatile mode and a volatile mode, include Japanese Patent Laid-Open Nos. 5996/1991, 283079/1991 and 283176/1991.
The inventor of this invention has invented a semiconductor memory device with a novel function, which considers drawbacks that a major part of the current consumption in DRAM (dynamic RAM) is used in the refresh operation and that the polarization characteristic of the ferroelectric memory using the ferroelectric capacitor deteriorates as the number of rewriting operations increases and which solves these two drawbacks by combining them together.